`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    19:12:19 07/05/2015 
// Design Name: 
// Module Name:    clk_div 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
//div a F HZ clock to F/2 HZ
module clk_half(clk_in,clk_out);
  input clk_in;
  output clk_out;
  
  reg clk_out=0;
  
  always @(negedge clk_in) begin
    clk_out<=~clk_out;
  end
endmodule

//generate 5MHZ clock
module clk_5M(clk_50M,clk_5M);
  input clk_50M;
  output clk_5M;
  
  reg clk_5M=0;
  reg [2:0] count=3'b0;
  
  always @(negedge clk_50M) begin
    count<=(count==4)?0:count+1;
  end
  
  always @(negedge clk_50M) begin
    if(count==0) clk_5M<=~clk_5M;
  end
endmodule

//generate 190 HZ clock
module clk_190(clk_100M,clk_190);
    input clk_100M;
	 output clk_190;
	 
    clk_half uc1(clk_100M,clk_in1);
    clk_half uc2(clk_in1,clk_in2);
    clk_half uc3(clk_in2,clk_in3);
    clk_half uc4(clk_in3,clk_in4); 
    clk_half uc5(clk_in4,clk_in5);
    clk_half uc6(clk_in5,clk_in6);
    clk_half uc7(clk_in6,clk_in7);
    clk_half uc8(clk_in7,clk_in8);
    clk_half uc9(clk_in8,clk_in9); 
    clk_half uc10(clk_in9,clk_in10);
    clk_half uc11(clk_in10,clk_in11);
    clk_half uc12(clk_in11,clk_in12);
    clk_half uc13(clk_in12,clk_in13);
    clk_half uc14(clk_in13,clk_in14); 
    clk_half uc15(clk_in14,clk_in15);
    clk_half uc16(clk_in15,clk_in16);
    clk_half uc17(clk_in16,clk_in17);
    clk_half uc18(clk_in17,clk_in18);
    clk_half uc19(clk_in18,clk_190);
 
endmodule
